1. Field of the Invention
The present invention relates to a semiconductor integrated circuit such as a memory, a photoelectric converting device, a signal processing device or the like adapted for use in various electronic appliances, and more particularly to a semiconductor device featured in the electrode structure of functional elements and a method for producing the same.
2. Related Background Art
For providing a highly integrated semiconductor circuit device, the development of miniaturized functional elements, such as a MOS transistor with a submicron gate length, has been found desirable in recent years. As a specific example, a MOS transistor with a gate length of 0.8 .mu.m occupies an area of ca 20 .mu.m.sup.2, suitable for a high level of integration.
However the higher level of integration achieved by the miniaturization of functional elements has not necessarily lead to the anticipated satisfactory characteristics. Such discrepancy has been considered attributable to the method for producing such functional elements, and the efforts to solve such drawback has inevitably been directed to the improvement in such producing method. Stated differently, the predominant perception has been that the preparation of a satisfactorily functioning element in stable and reproducible manner is an important factor for the improvement of production yield.
However, the detailed investigation of the present inventors on the element structure and on the producing method therefor has revealed that a novel structure in the electrodes and/or the wirings therefor can achieve a finer geometry and a higher level of integration, with improved performance. This fact will be explained in the following, taking a MOSFET and a planar CMOS transistor as examples.
FIG. 1A is a schematic plan view of an example of the conventional function element, and FIG. 1B is a schematic cross-sectional view along a line A--A' in FIG. 1A.
There are illustrated an n-type semiconductor substrate 1, and a p.sup.- -type semiconductor area (p.sup.- -well) 2, in which are formed a drain area 3 and a source 4 both of an n.sup.+ -type semiconductor, and a sub area for ohmic connection of the p.sup.- well 2 with an electrode. Above a channel area in the p.sup.- well 2, there is provided a gate electrode 6 across a gate insulation film, and an n-channel MOSFET is thus formed. A drain electrode 7 and a source electrode 8 respectively contact with the drain area 3, and with the source and sub areas 4, 5 through contact holes formed in an insulation layer 9,
Multi-terminal elements, such as functional elements, are often used with a fixed potential at a terminal. The above-explained MOSFET is used with the source and sub areas thereof maintained at a same potential. For this purpose, the sub area 5 is positioned horizontally next to the source area 4 across a field insulation film 10, and said source area 4 and sub area 5 are short-circuited by the source electrode 8 connected through the contact holes.
Such structure requires a plurality of field insulation films 10 and contact holes positioned in the horizontal direction, thus occupying a large area, and cannot achieve a sufficiently high level of integration even if a fine geometry can be realized.
For resolving the above-mentioned drawback, there is proposed a semiconductor device as shown in FIGS. 2A and 2B, which are respectively a schematic plan view and a schematic cross-sectional view along a line B--B' in FIG. 2A. In this structure, the source area 4 and the sub area 5 are positioned in mutually contacting manner, thereby dispensing with the field insulation film therebetween and requiring only one contact hole for said two areas, instead of one contact hole for each area.
However, even in this structure, the horizontal positioning of the source area 4 and the sub area 5 requires an excessive surface area. Also the contact hole requires a certain large diameter for achieving sufficient short-circuiting of the source area 4 and the sub area 5, so that the design freedom of the production process is difficult to increase.
In the following there will be explained an example of the planar CMOS transistor.
The logic circuit in an integrated circuit requires functional elements with features such as possibility for a high level of integration, a high-speed operation, a low power consumption etc., and the planar CMOS transistors have been recently used as the elements meeting such requirements for constituting the logic circuit. FIG. 3 schematically illustrates the structure of an inversion logic circuit composed of conventional planar CMOS transistors.
On a p-type substrate 501, there are formed an n.sup.- layer 502, a p.sup.- -layer 503, a LOCOS oxide film 504, and an interlayer insulation film 505. The PMOS transistor includes an n layer 506 for obtaining he substrate potential, a p drain layer 507 and a p.sup.+ source layer 508, while the NMOS transistor includes an n.sup.+ source layer 509, an n.sup.+ drain layer 510 and a p.sup.+ layer 511 for obtaining the substrate potential. There are further provided a gate oxide film 512, a gate electrode 513 for the PMOS transistor and a gate electrode 514 for the NMOS transistor.
The drain 507 and the n.sup.+ layer 506 of the PMOS transistor are given a highest potential, while the drain 510 and the p.sup.+ layer 511 of the NMOS transistor are given a lowest potential. The gate electrodes 513, 514 of the PMOS and NMOS transistors are mutually connected by a metal wiring to constitute an input terminal, while the sources 508,509 of said transistors are mutually connected by a metal wiring to constitute an output terminal, whereby an inversion logic circuit is constructed.
When a voltage equal to or higher than V.sub.th of the NMOS transistor, for example the highest potential, is applied to the gate electrodes 513, 514, a channel is formed below the gate of the NMOS transistor, whereby the drain 510 and the source 509 are connected. Thus an electron current flows through said channel, thus maintaining the output terminal at the lowest potential.
Then, when a voltage equal to or lower than (highest potential+V.sub.th of PMOS transistor), for example the lowest potential, is applied to the gate electrodes 513, 514, a channel is formed below the gate of the PMOS transistor, whereby the drain 507 and the source 508 thereof are connected. Thus a hole current flows through said channel, thus maintaining the output terminal at the highest potential.
The inverter function is thus realized, as the output terminal is maintained at the lowest or highest potential respectively when the highest or lowest potential is given to the input terminal.
In such conventional CMOS transistors, the device dimension is reduced by miniaturization of the gate length, contact holes and wiring width. However such conventional structure requires formation of gate areas on the surface, and isolation of the NMOS and PMOS transistors by a LOCOS oxide film, so that the device dimension has a limitation and a further reduction in size is difficult to achieve.